In recent years, in the semiconductor industry, a 3D stacking technology is developed to shorten the wiring between chips, reduce the sizes of devices, and help to construct a complete 3D chip structure. Through-substrate vias (TSV) are key components for connecting vertically stacked chips in the 3D stacking technology.
An interposer can be disposed to replace the wire packaging technique for electrically connecting heterogeneous chips. Even though through-silicon vias (TSV) and a redistribution layer (RDL) of optimal dimension ratios can be realized in an interposer along with the development of the 3D stacking technology, many costly semiconductor process steps need to be performed repeatedly to achieve the TSV and the RDL of the optimal dimension ratios. As a result, the manufacturing cost cannot be effectively reduced.